The present invention relates to PLL (Phase-Locked Loop) modulation circuits, and more particularly to a frequency modulation circuit using a PLL for data communications.
Frequency modulation using a PLL circuit is, in general, carried out using a system as shown in FIG. 1. In FIG. 1, reference numeral 101 designates a reference oscillator. The oscillation output of the reference oscillator 101 is applied to a phase comparator 104. The output of a VCO (Voltage-Controlled Oscillator) is applied to a frequency divider 103, the frequency division output of which is applied to the phase comparator 104. Thus, the oscillation output of the oscillator 101 and the frequency division output are subjected to phase comparison. The comparison output of the phase comparator 104 is applied as a control signal through an LPF (Low-Pass Filter) 105 and an adder 106 to the VCO 102. Further, a logic circuit 107 provides logic data as a modulating signal. The logic data is subjected to level conversion by a level converter 108 and the result applied to the adder 106. Accordingly, the logic data is superposed on the output of the LPF 105 in a DC mode so as to be used as the control signal for the VCO 102. Thus, an FM signal corresponding to the logic data is provided at the output of the VCO 102.
If the PLL modulation circuit is employed for data communication, since the modulating signal is the output of the logic circuit 107, it is necessary to convert the logic level (such as a TTL level) into a VCO control signal level by means of the level converter 108.
A specific example of the level converter 108 is shown in FIG. 2. In FIG. 2, the TTL level output signal of the logic circuit 107 (FIG. 1) is applied through an input terminal 210 to an input buffer 201 and is amplified by a first stage amplifier including a transistor 202 and resistors R.sub.1, R.sub.2 and R.sub.3. The output of the amplifier is applied through a coupling capacitor C.sub.1 to the second stage amplifier made up of a transistor 203 and resistors R.sub.4 through R.sub.7. The output of the second stage amplifier is applied through a coupling capacitor C.sub.2 to one input terminal of the adder 106, composed of an operational amplifier 204 and resistors R.sub.8 and R.sub.9, where it is added to the voltage V.sub.t at a terminal 211, which is the output of the LPF 105. The addition output V.sub.t ' is provided at a terminal 212 and is employed as the control signal for the VCO 102.
FIGS. 3A to 3C show voltage waveforms in the circuit of FIG. 2. More specifically, FIG. 3A shows the waveform of the logic input data at the terminal 210, which has a logic level in the range of 0 to 5 V in the case of a TTL level. FIG. 3B shows the waveform of the output of the capacitor C.sub.2, which has equal levels above and below half the supply voltage V.sub.cc. FIG. 3C shows the waveform of the output V.sub.t ' of the adder 106, which has equal levels above and below the output V.sub.t of the LPF 105.
The circuit shown in FIG. 2 is disadvantageous in that, since a.c. coupling is employed, the output voltage may be varied by the asymmetrical d.c. component of the modulating data itself. This variation, which depends in magnitude on the a.c. coupling time constant, cannot be eliminated. That is, if the time constant is increased, the time during which asymmetrical characteristics are present is increased at the beginning of a data burst, while if the time constant is decreased, unwanted local (short-term) waveform distortion occurs.
FIGS. 4A to 4D show d.c. variations in the circuit shown in FIG. 2. In FIG. 4A, the sign arrangement is such that the balance of 1s and 0s is one-sided; however, with respect to the sign arrangement, the waveform as shown in the FIG. 4B can be obtained by taking the output of the capacitor C.sub.2 in the circuit of FIG. 2 into account. At the rear stage of the capacitor C.sub.2, the operation is such that the average value of the input signal becomes the reference voltage, and therefore, in the string of 0s, the voltage approaches the reference voltage and the noise margin is decreased. By applying this signal to the frequency modulation input terminal, the frequency is gradually changed.
When burst-signal-like data as shown in FIG. 4C is applied to the circuit shown in FIG. 2, a response as shown in FIG. 4D is obtained. This takes place according to the same principle as that of the above-described operation; that is, it is due to the capacitor's differential operation.
The two operations may be avoided by changing the capacitance value of the capacitor. By increasing the capacitance, with respect to the operation described with reference to FIG. 4B, d.c. variations can be suppressed for a certain period of time, but with respect to the response described with reference to FIG. 4D, the transient effects are increased. It is evident that the operation described with reference to FIG. 4B is greatly affected by reducing the capacitance of the capacitor.
Thus, when a.c. coupling is used, if the data to be modulated is a burst-like signal, theoretically it is impossible to avoid the effects of the coupling capacitor.